I. Field of the Disclosure
The technology of the disclosure relates generally to through-silicon vias (TSVs) for three-dimensional (3D) integrated circuits (ICs) (3DICs), and more particularly to the detection of silicon substrate surface cracks therein.
II. Background
Computing devices have become commonplace throughout society. The increasing presence of such computing devices has accelerated in part because of the increasing functionality and versatility of such computing devices. This increase in functionality and versatility has been enabled by providing increasingly powerful processing capabilities in small packages as loosely recognized by Moore's Law. As a result, companies have been trying to increase functional integration more quickly than Moore's Law or circuit performance requirements. However, pressures to increase processing capabilities while decreasing the size of integrated circuits (ICs) have strained conventional manufacturing processes, especially as node size within the ICs has been reduced to low nanometer (nm) dimensions (e.g., <20 nm). Thus, there has been a proliferation of interconnect schemes such as silicon in package, package-on-package, and system-in-a-package (SiP) multi-chip modules (MCMs) schemes to decrease the size of ICs.
Current miniaturization techniques include three-dimensional (3D) integrated circuits (3DICs). In 3DICs, ICs are arranged in an x-y-z coordinate system in a plurality of layers or tiers (referred to as “layers” hereinafter). Such an arrangement achieves higher device packing density, lower interconnect delay, and lower costs than a two-dimensional (2D) arrangement (i.e., ICs arranged in an x-y coordinate system in a single layer). Techniques to manufacture or form 3DICs include some form of through-silicon vias (TSVs) to effectuate electrical connections between the stacked wafers or dies (i.e., connections between ICs arranged in the z direction layers of the x-y-z coordinate system). In this regard, FIG. 1 illustrates an example of a 3DIC 100. The 3DIC 100 includes a plurality of stacked, fabricated IC layers 102(1)-102(N) that each include electrical circuits 104. TSVs 106 are fabricated in the 3DIC 100 to interconnect the electrical circuits 104 between the different IC layers 102(1)-102(N).
Defects in any of the stacked IC layers 102(1)-102(N) can result in the 3DIC 100 in FIG. 1 being defective due to the interdependence of the 3DIC 100 on the various IC layers 102(1)-102(N). Defects may be caused by, for example, thermal expansion of a TSV 106 due to a coefficient of thermal expansion (CTE) mismatch between the TSV 106 and its surroundings. This CTE mismatch-induced stress between the TSV 106 and its surroundings may generate radial cracks propagating from the TSV 106 towards the silicon substrate surface during a back-end of line (BEOL) process employed during fabrication of the 3DIC 100, as BEOL processes include one or more thermal cycles. In this regard, FIG. 2A illustrates a Scanning Electron Microscope (SEM) view of a TSV 106 in the 3DIC 100 in FIG. 1 that has cracked during fabrication due to thermal expansion due to CTE-mismatch-induced stress. FIG. 2B shows a portion of the TSV 106 in FIG. 2A and a radial crack 200 in the silicon substrate surface adjacent to the TSV 106 caused due to thermal expansion of the TSV 106. If a crack, such as the radial crack 200, reaches a nearby device disposed on the substrate (e.g., a transistor), the radial crack 200 may damage the nearby device, which may render the 3DIC 100 inoperable.
In this regard, 3DIC designs typically provide for a keep-out-zone (KOZ) to be observed in a radial area around TSVs during 3DIC fabrication to avoid CTE mismatch-induced cracks from damaging adjacent silicon substrate surfaces. However, if a TSV crack propagates beyond the KOZ, it may jeopardize the reliability of the devices along its propagation path, and therefore, the corresponding stacked wafer and 3DIC system. Although a large KOZ area would increase the reliability and/or fabrication yield of 3DICs, it is desired that a KOZ is kept small to conserve area in the 3DIC.
A technique for testing a 3DIC for TSV cracks is to indirectly detect critical cracks by checking for various device and circuit level faults such as timing violations, stuck-at faults, etc. caused by the TSV cracks. However, with limited testing coverage, large number of TSVs, and various possible crack propagation directions, such a technique, may fail to identify every chip with TSV cracks. In other words, a direct TSV crack detection technique is imperative to guarantee shipping only TSV-crack-free chips.
Traditionally, direct detection of TSV cracks has been primarily based on microscope or X-ray diffraction analysis. However, such techniques are time-consuming and cost-prohibitive for large-scale 3DIC production. Accordingly, there is a need to provide practical, relatively fast, and cost-effective techniques for direct detection of TSV cracks in 3DICs' silicon substrate surfaces.
Furthermore, such traditional techniques for direct detection of TSV cracks in 3DICs' silicon substrate surfaces can only indicate that at least one of the TSVs is cracked, not which doped ring is cracked. Accordingly, finding a TSV crack is conventionally addressed by discarding the corresponding 3DIC, and reducing manufacturing yields. Further still, such traditional techniques for direct detection of TSV cracks in 3DICs' silicon substrate surfaces may only be applied during the manufacturing cycle. If a TSV crack develops after the corresponding 3DIC is embedded in a system, the TSV crack may cause the entire system to be discarded, increasing costs and decreasing customer satisfaction. Therefore, there is a need to provide ways to repair, in real-time, a 3DIC that has been determined to contain TSV cracks.